RTL verification

Adantic has considerable knowledge of RTL design verification to a very high standard. Using the latest methodologies, Adantic can help ensure that your design meets its requirements.

A complete bespoke self-testing environment can be designed and implemented by Adantic to meet customer requirements. Example experience includes:

• OVM (Open Verification Methodology) testbench design and implemention
• VMM (Verification Methodology Manual) testbench design and implemention
• Code coverage, functional coverage and checks
• Constrained random testing, self-checking and automated regression
• Formal verification using PSL
• VHDL, Verilog and SystemVerilog testbench design
• Code assertions, both during RTL implementation and retro-fitted assertions

Adantic will help identify customer needs, provide testbench documentation and organise the creation of block- and system-level testbenches, with maximum code re-use and automation. Adantic specialises in SystemVerilog testbenches using OVM, promoting modular verification IP and a structured approach to design verification.

Please contact Adantic for further information.