RTL design

Adantic specialises in FPGA and ASIC design work using VHDL, Verilog and SystemVerilog.

Adantic has experience in designing for a range of FPGA vendors, including Xilinx, Altera, Actel and Lattice, using a variety of design tools on Linux, Solaris and Windows.

Example areas of expertise include:

• High speed interface controllers
• Complex algorithms (e.g. cryptographic functions)
• Communication protocols (Ethernet, IPv4, IPv6, 3G)
• Data processing applications
• Embedded processor design
• Internal messaging systems

Adantic also has significant experience in implementing process flows and tool usage guidelines for FPGA and ASIC designs. In particular, the following tools have been used extensively:

• Modeltech ModelSim PE/SE/Designer
• Synopsys VCS
• Cadence IUS
• Mentor Graphics HDL Designer/Author
• Synplicity Synplify Pro
• Vendor place and route tools
• Vendor debug tools (e.g. Xilinx ChipScope Pro)
• Advanced verification tools (e.g. Averant Spyglass)

Please contact Adantic for further information.